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Silicatec will elevate the knowledge of fresh technology graduates
through our specially designed programs, in the domain of VLSI with
the aim of immediate fitment into work organization & culture
reducing the cycle time of making or transforming an entry level employee
to a productive employee. Our programs are currently taught at Bhubaneswar
branch but our flexible yet comprehensive curricula can be available
at any location in many formats to meet your needs
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 PROGRAMS
OFFERED
Silicatec's offers a wide range of programs at varying levels be
it switching careers or adding skills to take your current career
up the next level.
1) PG Diploma in VLSI Logic Design
(a) REGULAR: 5 Months, Fee: Rs 30,000
- Introduction to VLSI Design
- Introduction to HDL (Verilog, VHDL)
- FPGA design flow
- ASIC/SOC design flow
- RTL Design (Verilog)
- Synthesis & STA
- CMOS VLSI Design
- FPGA architecture and FPGA as a system component
- Introduction to Verification
- Introduction to HVL (System Verilog)
- Advanced Verification techniques
- Scripting Languages
- Protocols Training (AMBA, USB. PCI. Etc.)
- Individual Project (Industry Standard Projects: Documentation,
Architecture Design, HDL Description, Simulation and Synthesis)
Eligibility: B.E/B.Tech, M.E/M.Tech Engineering,
B.Sc/M.Sc. (Electronics/Physics)
(b) Short Term leading to PG diploma in
VLSI Logic
Design
Complete Level 1, Level 2 and Level 3 of Short term courses at your
pace. After successful completion of these courses, earn PG Diploma.
Refer to Short term course lists.
Eligibility: 2nd, 3rd and 4th year BE/B.Tech students. B.Sc
/M.Sc(Electronics/Physics) students.The short term courses can be
completed either on campus or attend Online courses.
2) SHORT
TERM Courses, ASIC Logic Design and
Verification (Front-end)
Available:
a) Regular time on Week days
b) Part time Morning/Evening/Weekends
LEVEL 1: Digital Logic Design using HDL
Duration: 4 weeks, Fees: Rs 6,000
- Introduction to Digital Electronics
- Combinational & Sequential Circuit
- Design Finite State Machine (FSM)
- Introduction to VLSI Design
- FPGA design flow
- ASIC/SoC design flow
- Introduction to HDL (Verilog, VHDL)
- Standard coding style for team environments
- Simulation and Synthesis
LEVEL 2: Advanced Digital Circuit and CMOS
VLSI Design
Duration: 6 weeks, Fees: Rs 9,000
- Advanced Design Issue (metastability, noise margins, power,
skew, timing consideration)
- Static Timing Analysis
- Effective coding style
- ASIC Design Issues (Testability, test methodologies)
- FPGA architecture and FPGA as a system component
- CMOS VLSI Design
- Low Power Design
- Introduction to Verification
LEVEL 3: Advanced Verification with System
Verilog &
Project
Duration: 10 weeks, Fees: Rs 15,000
(Level 3-A) Advanced Verification with System Verilog
Duration: 5 weeks
- Advanced Design Issue (metastability, noise margins, power,
skew, timing consideration)
- Static Timing Analysis
- Effective coding style
- ASIC Design Issues (Testability, test methodologies)
- FPGA architecture and FPGA as a system component
- CMOS VLSI Design
- Low Power Design
- Introduction to Verification
(Level 3-B) Project
Duration: 5 weeks
- Protocols Training
- Introduction to Bus Protocols (AMBA, AHB)
- Introduction to Peripheral Bus (USB)
- Introduction to System Bus (PCI)
- Project (Industry Standard Projects: Documentation, Architecture
Design, HDL Description, Simulation and Synthesis)
3) Short
Term summer courses in VLSI
Duration : 120 Hours, Fees : Rs 5,500
- Introduction to Digital Design
- Introduction to EDA Tools
- Advanced Digital Issues (Timing Analysis)
- Introduction to HDL (Verilog, VHDL)
- Design of combinational and sequential circuits using Verilog
- Design Finite State Machine (FSM) using Verilog
- Synthesis
- Verification Methodology
- Individual Projects
Eligibility: 2nd, 3rd and 4th year BE/B.Tech students. B.Sc
/M.Sc(Electronics/Physics) students. The short term courses can
be completed either on campus or attend Online courses.
4) On-line
courses in VLSI Front-end Design New
Duration: 120 Hours, Fees: Rs 5,000
- Introduction to Digital Design
- Introduction to EDA Tools
- Advanced Digital Issues (Timing Analysis)
- Introduction to HDL (Verilog, VHDL)
- Design of combinational and sequential circuits using Verilog
- Design Finite State Machine (FSM) using Verilog
- Synthesis
- Verification Methodology
- Individual Projects
Eligibility: 2nd, 3rd and 4th year BE/B.Tech students. B.Sc
/M.Sc(Electronics/Physics) students. The short term courses can
be completed either on campus or attend Online courses.
5) ASIC
Physical Design (Backend Design flow)
Duration: 120 Hours, Fees: Rs 5,500
- Introduction to CMO
- Physical design flow
- Layout & stick diagrams
- Floor plan, Placement, Optimization & Routing
- Introduction to Fabrication
Eligibility: 2nd, 3rd and 4th year BE/B.Tech students. B.Sc
/M.Sc(Electronics/Physics) students. The short term courses can
be completed either on campus or attend Online courses.
6) Free
Seminars/Information session on VLSI
Keep checking for the announcement
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